DDR and D2D PHY System Design Engineer (San Diego or Santa Clara)

Location: San Diego, California, United States of America, Santa Clara, CA, USA

Department: ASICS Engineering

Work Location: onsite

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

QCT mixed-signal IP design team is looking for skilled system architect to help design high-speed, high-performance and low-power LPDDR and D2D PHYs for Qualcomm’s products targeted for 5G, AI/ML, compute, and automotive applications. This role is part of the LPDDR and D2D PHY design team. You’ll help with system design, building, and testing—starting from early ideas all the way to final chip production and validation.

Responsibilities:

• Analysis and ownership of system and architecture
• Development of system timing budgets, both on-die and off-chip.
• Signal and power integrity
• Lead and deliver best-in-class solutions for product needs

 

Required for this Role:

• 10+ years in DDR and/or D2D PHY design
• Expertise in SOCAMM/DIMM long-channel signal integrity, and power delivery
• Strong knowledge of system architecture, link-budgets, trainings, and integration
• Solid understanding of design-for-yield and production challenges in high-speed links
• Strong communication skills; proven ability to collaborate across global teams

 

Preferred Qualifications

• Hands-on experience from architecture through production in server-class designs
• System understanding of memory and D2D links for high-performance compute
• Experience in latest process technology nodes and mixed-signal designs
• Unix/Perl/TCL scripting (must be comfortable with writing scripts)

 

Educational Requirements

• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering

 

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

 

Pay range and Other Compensation & Benefits:

$164,000.00 - $246,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.