CPU RTL/AI Micro-Architect - AI Development

Location: Austin, Texas, United States of America, Santa Clara, CA, USA

Department: CPU Engineering

Work Location: onsite

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > CPU Engineering

General Summary:

Qualcomm is a company of inventors pushing the boundaries of high‑performance compute. Building on a legacy of industry‑leading innovation, we are extending our leadership into the datacenter, delivering next‑generation CPU solutions that combine world‑class performance, power efficiency, and scale.

As AI transforms every layer of computing, Qualcomm is at the forefront of defining how CPUs are designed, optimized, and deployed for AI-driven and cloud-scale workloads. Central to this transformation is our investment in advanced design methodologies and AI‑augmented engineering workflows—enabling faster innovation cycles, deeper design insight, and higher-quality silicon.

We are driving the evolution toward agentic AI-assisted design, where intelligent tools are embedded across the engineering lifecycle—from architecture exploration to RTL development, analysis, and debug. This approach enhances engineering productivity while preserving the deep expertise and rigor required to deliver industry-leading CPU designs.

This is the next phase of compute innovation—where high-performance CPU architecture meets AI-driven design practices for the datacenter era.

This is the Invention Age — and this is where you come in.

Roles and Responsibilities

AI-Enhanced RTL Development & Workflow Innovation

• Apply and extend existing internal AI tools and agent-based workflows to enhance RTL design productivity

• Develop AI-driven capabilities for:

  • RTL code review and quality analysis (readability, methodology adherence, structural correctness)

  • Spec ↔ RTL alignment, ensuring consistency between microarchitecture documentation and implementation

  • Automated debug acceleration, including waveform triage and root-cause identification

• Integrate AI into standard RTL development loops rather than creating parallel flows

RTL Analysis & Insight Generation

• Enable AI-assisted analysis for:

  • Timing, power, and area (PPA) tradeoffs

  • Microarchitectural bottlenecks and inefficiencies

  • Code-level improvements for maintainability and reuse

• Develop mechanisms to surface actionable insights early in the design cycle, improving iteration velocity

Workflow Integration & Scaling

• Embed AI capabilities into existing toolchains and methodologies (lint, synthesis, simulation, debug)

• Collaborate with CAD, DV, and global design teams to scale AI-enabled workflows across programs and geographies

• Contribute to cross-team AI initiatives and working groups to align efforts and maximize reuse of internal capabilities

Methodology & Best Practices

• Evolve RTL methodology by integrating AI-assisted best practices into:

  • Coding standards and review processes

  • Debug and analysis workflows

  • Documentation and specification alignment

• Ensure solutions align with Qualcomm’s established RTL principles of readability, maintainability, and cross-discipline usability

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Preferred Qualifications

• Strong knowledge in AI/LLM-based engineering tools:

  • Agentic tools (i.e. Codex, Claude Code)

  • Agent-based AI development (prompting, chaining, orchestration)

• Solid experience with:

  • Verilog/SystemVerilog (or VHDL) RTL design

  • Simulation, waveform debug, and verification tools

• Knowledge of CPU Design Techniques:

  • Logic design principles and timing/power implications

  • Low-power microarchitecture techniques

  • High-performance design tradeoffs

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

 

Pay range and Other Compensation & Benefits:

$179,000.00 - $268,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.