Chiplet and 3D Stacking Engineer, Senior Staff

Location: Hsinchu City, Hsinchu City, Taiwan

Department: ASICS Engineering

Work Location: onsite

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible and drives communication and data processing transformation to help create a smarter, connected future for all. In this journey, Qualcomm is evolving into an “AI-first” intelligent-edge powerhouse, combining high-performance, low-power compute and seamless connectivity while pushing intelligence closer to users through ultra-efficient, on-device AI that ensures privacy, personalization, and real-time responsiveness. This is the Invention Age - and this is where you come in.

Keywords:

3DIC, STCO, PPAC, Physical design, Chiplet, Heterogeneous Integration

Key Responsibilities:

• Work with system architecture and SoC design teams, define and assess 3DIC process technology requirements and roadmap

• PPAC assessment for System-Technology Co-Optimization (STCO) for new product development

• Foundry interface for 3DIC physical design flow and key design rule definitions

• Establish dependency of 3D process solutions on key chip architecture and design KPI and co-optimize 3D solutions accordingly.

• Pathfinding and development of chiplet physical design methodology and PDK development

• 3D DRAM and Cache SRAM Architecture evaluation for AI and other Compute workloads

• Custom DRAM integration technology evaluation and pathfinding

Desired Skillset/Experience:

• Experience with 2.5D and 3D STCO and pathfinding

• 2.5 and 3D Chip partition and dependencies on Product KPI like performance, power, chip and beachfront area, chip-chip communication metrics, power grid etc.

• System and/or chip-level architecture and physical design experience for 3D cache partitioning (a plus)

• Physical design experience with SoIC and/or CoWoS

• Experience with 2.5D/3D IC design flow and PDK development

• Familiarity with heterogeneous integration processes such as hybrid bonding, wafer bonding, TSV, backside metallization

• Process development and/or system and product development experience with advanced technology (sub 4nm) and its PPAC assessment

• Custom layout, svrf, scripting skills

• Hands-on experience with DRC, LVS, PEX (a plus)

Additional Qualifications: 

• Ability to work across teams and BUs

• Ability to work without supervision and as part of a team

• Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach

• Advanced data analysis and interpretation skills are required.

Minimum Qualifications

•  Bachelor's degree in Science, Engineering, or related field and 5+ years of AI relevant System and technology or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 4+ years of AI relevant System and technology or related work experience.
• OR
• PhD in Science, Engineering, or related field and 3+ years of AI relevant System and technology or related work experience.

 

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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