CAD Implementation Engineer

Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of RTL2GDS solutions for the Snapdragon chips powering billions of mobile devices.  The position requires ASIC Physical Design or CAD development experience to define and develop implementation tools and methodologies for PPA, Quality and shortening design cycle time, in close collaboration with Synthesis and Physical design teams.

This role’s responsibilities will include:

• Improve the SoC Implementation methodology for diverse Mobile, Compute, AI, IoT Snapdragon chips.

• Develop CAD tools for optimization of Synthesis, Floorplan, Place and Route and Design closure.

• Project Global CAD Implementation solutions to the Snapdragon design teams, analyze their requests and interface with Flow development team to implement new solutions and fixes.

• Collaborate with core and SoC design team to develop solution for advanced multi-die implementation and advanced process nodes.

• Collaboration with design teams

• Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement.

Preferred Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.

• 2-5+ years of experience in Synthesis, Place and Route or/and Floorplanning of SoCs. 

• 2-5+ years of experience of CAD solution development applied to Physical Design.

• 2-5+ years of experience with scripting tools and programming languages: Python and TCL preferred.

Principal Duties and Responsibilities:

• Product Engineer for the Synthesis and Place and Route Global CAD Solution using the state-of-the-art foundry tech nodes, including the task of facing design teams in solution-finding meetings, presenting new technologies and following up on problems and solutions.

• Participate to the development of the RT2GDS flow, including the tuning of design recipes to address specific Power-Performance-Area (PPA) objectives on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.

• Interface and drive EDA vendor Application Engineers on the resolution of Synthesis and Place and Route problems faced by the Snapdragon design teams.

• Participate to the specification of new CAD solutions addressing the PPA requirements of the design teams.

• Deep dive on implementation issues, such as congestion hot spots, pin access related design rules violations, suboptimal clock tree synthesis, high leakage or dynamic power dissipation, long cell legalization runtime.