ASIC Design Engineer, Low Power AI Subsystems

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General Summary:

What we are doing has not been done.

Shape the future of low power AI subsystems.

Push the boundaries on features and performance.

Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues.

As we are pioneer new and/or improved functionality, innovate to minimize power consumption.  Make a difference, join a team on the cutting edge and become an integral part of Qualcomm’s growth and momentum.

We are looking for an ASIC Design Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and context aware applications. We are open to all levels of applicants, with responsibility being commensurate with experience. We are looking for applicants who thrive when presented with constant opportunities for learning and growth and who want to have a large impact on our team.

As part of our team your responsibilities would include:

• Design high speed, low power digital hardware solutions
• Contribute to definition, micro-architecture and documentation
• Collaborate closely with the Verification team to test, debug and close coverage on the design
• Evaluate synthesis results to verify the design meets the speed, power and area targets
• Support internal hardware integration, SW teams around the world
• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision
• Use of various design tools (VCS, DC, Linting, CDC, LEC, CLP etc.) to check and improve design quality
• Provide ideas and further the innovation of ASICs, IP cores, and process flows

Requirements:

• Professional or academic ASIC hardware design and/or implementation experience. New graduates should have ASIC design internship or co-op experience.
• Proficiency with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
• Good understanding of ASIC/VLSI concepts
• Experience in logic synthesis using Synopsis and/or Cadence tools.

Preferred Qualifications:

• 2+ years of ASIC hardware design related experience
• Working knowledge of UPF specification
• Experience with power analysis, power modeling and low power RTL design.
• Experience with clock domain crossing techniques
• Experience with a subset of DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)
• Experience with design rule check (Spyglass, etc.), Formal verification (Formality, LEC, etc.) and/or Power analysis and simulation
• Scripting skills (Python , PERL, TCL or C)
• Knowledge of bus interface protocols (APB, AHB, AXI) 
• Experience with post-silicon debug
• Experience with UVM
• Experience with automotive safety concepts and standards such as ISO26262

Minimum Qualifications:

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