Post-Silicon Validation Engineer

Location: Santa Clara, California

Department: External - Client Requirement

Role Overview

• Lead silicon bring-up, post-silicon validation, and deep debug of next-generation AI accelerator chiplets, including validation of high-speed interfaces such as PCIe Gen5, LPDDR5, and die-to-die interconnects.

• Define and execute comprehensive validation and bring-up strategies, building automated, self-checking test frameworks with firmware- and kernel-level instrumentation and logging.

• Develop embedded firmware and host-side test software to stress, validate, and characterize high-speed interfaces across multiple system configurations.

• Work hands-on in the lab, partnering with the team to set up and utilize advanced debug and test equipment to support efficient validation and issue resolution.

• Collaborate closely with hardware, software, validation, test, and operations teams, including support for ATE and complex HW/SW debug efforts.

Qualifications

• BS/MS in Electrical or Computer Engineering with 15+ years of experience working on high-performance SoCs.

• Proven experience in system and AI accelerator bring-up and post-silicon debug.

• 5+ years of embedded software, firmware, or RTOS development experience.

• Strong familiarity with high-speed serial protocols (PCIe Gen3/4/5) and/or high-speed memory technologies (LPDDR3/4/5 or similar I/O standards).

• Excellent debugging, communication, and cross-functional collaboration skills, with the ability to work effectively across diverse engineering teams.