Senior Static Timing Analysis (STA) Engineer
Location: Tianjin (Teda)
Time Type: Full time
Job Description
Overview:
Expect experienced Senior STA Engineer to join our IC design team. This role will lead timing signoff activities for complex SoC projects, ensuring robust timing closure across multiple process, voltage, and temperature corners. Will collaborate closely with front‑end and back‑end design teams to drive high‑quality, high‑performance chip implementation.
Key Responsibilities:
- Own full‑chip static timing analysis and signoff for advanced‑node SoC designs.
- Develop and maintain STA constraints (SDC) and timing methodologies.
- Perform block‑level and top‑level timing analysis, debug violations, and guide design teams toward closure.
- Work with RTL, synthesis, and physical design teams to resolve setup/hold, clock skew, noise, and transition issues.
- Optimize timing through constraint refinement, logic restructuring suggestions, ECO guidance, and physical optimization feedback.
- Analyze and validate timing models, including Liberty (.lib), SPEF, and SDF.
- Support timing‑related signoff flows, including OCV/AOCV/POCV, crosstalk analysis, and MCMM timing closure.
- Provide technical leadership in methodology development, tool evaluation, and flow automation.
- Collaborate with cross‑functional teams (DFT, power, architecture) to ensure consistent timing across all design modes and corners.
- Mentor junior engineers on STA fundamentals, flow usage, and debugging techniques.
Qualifications:
- Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Strong English communication skills, including the ability to collaborate effectively with global teams and clearly articulate technical issues in English.
- 5+ years of hands‑on STA experience in SoC development.
- Strong proficiency with industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
- Solid understanding of timing concepts such as OCV/AOCV/POCV, clock tree synthesis, crosstalk, IP timing integration, and MCMM flows.
- Familiarity with synthesis, place-and-route, and ECO flows.
- Expertise with SDC constraints and timing debugging.
- Strong scripting skills in Tcl, Perl, Python, or Shell.
- Excellent problem‑solving abilities and communication skills.
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