Senior Principal Verification Engineer, Digital IP

Location: Bangalore

Time Type: Full time

Job Description

Job Title: Sr. Principal Verification Engineer

Primary Location: Bengaluru, India

Role Summary:

We are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design. 

MME's Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.

Job Responsibility:

• Responsible for the pre-silicon verification of IP modules or, IP subsystems
• Responsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
• Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• Responsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.
• Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.

Job Qualification:

• Degree in Electrical Engineering or Computer Science, with 12+ years of experience on IP/Sub-System Verification
• Prior experience as a tech lead or DV manager is strongly preferred
• Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
• Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
• High proficiency in Metric Driven Verification concepts, functional and code coverage.
• High proficiency in directed and constrained random methodologies.
• Good knowledge of formal verification methodologies and assertions.
• Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
• Excellent written and verbal communication skill. 
• Good knowledge in scripting like Perl, TCL or Python is a plus

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