Senior Principal Digital Design Engineer

Location: Sophia-Antipolis (Valbonne)

Time Type: Full time

Job Description

Job Summary
As a Senior Principal Digital Design Engineer at NXP Semiconductors France SAS, you will be a key technical leader in the design, verification, and implementation of complex digital circuits for next-generation automotive and secure embedded control products. You will drive innovation and technical excellence within your team, contributing to the full lifecycle of digital design from specification to silicon validation.

Job Responsibilities
* Lead the architectural definition, micro-architecture, and RTL design of complex digital IP blocks and subsystems, ensuring performance, power, and area targets are met.
* Drive the functional verification strategy and execution, collaborating closely with verification teams to achieve robust coverage and bug-free designs.
* Mentor junior and senior engineers, providing technical guidance, design reviews, and fostering a culture of continuous improvement.
* Collaborate with system architects, software teams, and physical design engineers to ensure seamless integration and optimal system performance.
* Develop and maintain comprehensive design documentation, including specifications, design documents, and verification plans.
* Participate in pre-silicon and post-silicon validation activities, including debug and characterization, to ensure product quality and functionality.
* Identify and evaluate new design methodologies, tools, and flows to enhance productivity and design quality.
* Drive continuous improvement in design processes and quality metrics, contributing to best practices within the organization.

Job Qualifications
* Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
* 10+ years of experience in digital IC design with a strong track record of successful product delivery.
* Expert-level proficiency in Verilog/SystemVerilog RTL design and simulation.
* In-depth knowledge of digital design principles, including clock domain crossing (CDC), reset domain crossing (RDC), and low-power design techniques.
* Extensive experience with industry-standard EDA tools for RTL simulation, synthesis, formal verification, and static timing analysis.
* Strong understanding of embedded systems architectures, including processors, memory subsystems, and various communication interfaces (e.g., PCIe, Ethernet, USB, SPI, I2C).
* Proven experience in leading design efforts for complex IP blocks or subsystems.
* Excellent problem-solving, analytical, and debugging skills.
* Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams.
* Experience with scripting languages (e.g., Python, Perl, Tcl) for design automation and data analysis.
* Knowledge of automotive functional safety standards (e.g., ISO 26262) is a plus.

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