Senior Principal Analog Design Engineer PMU
Location: Caen, Sophia-Antipolis (Valbonne), Toulouse
Time Type: Full time
Job Description
The goal of the SCE (Secure Connected Edge) team within NXP is to become the leader in its market by leveraging its unique portfolio of IP from NFC and Secure Elements, NFC and UHF tags, WiFI, UWB and Bluetooth products to deliver solutions that are better than the sum of its parts.
NXP is a world leader in security, especially for mobile payment applications and continues to drive growth through innovation.
Working in a fast pace mobile environment, we are looking for outstanding engineers to join our global Analog Power Management team.
The role will also involve frequent communication with key customers for detailed reviews
Responsibilities
- Define key specifications, drive feasibility, design, and perform simulations of power management blocks such as regulators, bandgap and DC/DC Buck/Boost converters
- Provide accurate estimates for silicon area and performance
- Execute to meet challenging schedule while ensuring high quality
- Interface to physical design, digital, FW teams to provide support and guidance on the use of the analog blocks
- Own the power management macro from specification to production, including support of the validation and ATE teams to ensure that the performance and parameters are met
- Participate actively in peer reviews of analog blocks at IC and System level
- Interface to the customer during design reviews, issue root-cause and bug fixes
- Work with other teams on the project (Digital, Firmware, Layout, Test ) to ensure the success of the overall product
- Guide and develop junior and senior engineers
Profile
- Masters Degree in Electronic/Electrical Engineering
- Minimum of 12 years experience in the design of analog blocks and systems for power management
- Experience with technical design leading
- Proven track record in delivering working silicon for high volume products
- Solid fundamentals of transistor level integrated circuits and device physics.
- Knowledge of layout matching and parasitics, latch-up, ESD, etc.
- Demonstrate an innovative and creative attitude, taking initiative to propose and implement improvements
- Rigorous and methodical with good analytical skills for debugging issues in design and on silicon
- Familiarity with EDA design tools and Cadence design environment
- Knowledge of power management designs in various application types is desirable
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