NXP Semiconductors logo

Principal Digital IP Design Engineer

NXP Semiconductors

On-site
Munich
Full-time
Principal
10+ yrs
Salary not listedPosted 4w ago

Real job — pulled straight from NXP Semiconductors’s careers page · Verified July 17, 2026 · No reposts.

Job description

NXP Semiconductors is hiring a Principal Digital IP Design Engineer — a full-time, based in Munich role. Apply directly on NXP Semiconductors's careers page below.

Principal Digital IP Design Engineer (f/m/d)

Location: Munich

Time Type: Full time

Job Description

Business Line Description: 

Advanced Chip Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, micro-controllers, and networking. The Munich Digital IP team develops interface components, DSP subsystems, next generation AI/ML core and RISCV IPs.

Key Responsibilities:

  • Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), adhering to architectural specifications and performance requirements.
  • Collaborate closely with hardware and software teams, as well as architecture and system engineering teams, to understand IP functionality and system-level use cases to define features, interfaces and integrate digital blocks.
  • Develop high-quality, area-optimal, low-power RTL design using industry-standard hardware description languages (Verilog/SystemVerilog)
  • Complete design quality checks such as Lint, CDC/RDC, etc. using industry-standard tools.
  • Conduct IP-level design verification activities, including basic testbench development, simulation and debugging to ensure functional correctness.
  • Complete IP synthesis and basic timing analysis to meet timing, area and power targets.
  • Ensure IP design implementation is done according to design for testability (DFT) requirements.
  • Generate comprehensive design documentation and participate in design reviews.
  • Troubleshoot and resolve design issues throughout the development lifecycle.
  • Stay updated with the latest industry trends, tools, and methodologies in digital design.

Qualification:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
  • Minimum 10 years of experience in IP or subsystem design.
  • Solid understanding of microprocessor architecture, interconnects, and cache coherency mechanisms.
  • Hands-on experience with CPU design (proprietary cores, RISC-V, or AI/ML accelerators).
  • Experience in using AI-based tools to enhance development and design efficiency.
  • Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR).
  • Advanced knowledge of Verilog, SystemVerilog, and C/C++.
  • Proficiency in scripting languages such as Python, Perl, TCL, or Shell.
  • Experience in debugging designs in both pre-silicon (simulation/emulation/FPGA) and post-silicon environments.
  • Strong analytical and problem-solving skills.
  • Excellent written and verbal communication skills in English.
  • Basic conversational German is a plus.

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.

More information about NXP in Germany...

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Frequently asked questions

What skills are required for Principal Digital IP Design Engineer at NXP Semiconductors?

The required skills for Principal Digital IP Design Engineer at NXP Semiconductors include: Verilog, SystemVerilog, C++, Python, Perl, Shell, FPGA.

What is the seniority level for Principal Digital IP Design Engineer at NXP Semiconductors?

Principal Digital IP Design Engineer at NXP Semiconductors is a Principal level position.

How do I apply for Principal Digital IP Design Engineer at NXP Semiconductors?

You can view the full description and apply for Principal Digital IP Design Engineer at NXP Semiconductors on EchoJobs: https://echojobs.io/job/nxp-semiconductors-principal-digital-ip-design-engineer-f-m-d-btjf8.