Real job — pulled straight from NXP Semiconductors’s careers page · Verified July 17, 2026 · No reposts.
Job description
NXP Semiconductors is hiring a Lead DFT Engineer — a full-time, based in Noida role. Apply directly on NXP Semiconductors's careers page below.
Lead DFT Engineer
Location: Noida
Time Type: Full time
Job Description
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis. Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. . Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG). Effective communication and teamwork skills, with the ability to collaborate across functions.
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Frequently asked questions
What is the seniority level for Lead DFT Engineer at NXP Semiconductors?
Lead DFT Engineer at NXP Semiconductors is a Staff / Manager level position.
How do I apply for Lead DFT Engineer at NXP Semiconductors?
You can view the full description and apply for Lead DFT Engineer at NXP Semiconductors on EchoJobs: https://echojobs.io/job/nxp-semiconductors-lead-dft-engineer-5iapc.