NXP Semiconductors

Digital/Mixed-signal Design Intern

Tianjin
Verilog VHDL
Description

2026 Intern- Digital/Mixed-signal Design Intern

Location: Tianjin (Teda)

Time Type: Part time

Job Description

Responsibilities:

1. Design and verify digital block for Mixed-signal IP

2. Release digital IP component to SOC

3. Support SOC integration for Mixed-signal IP

4. Create thorough review documentation and follow established design flow

Requirements:

1. Master student in Electrical Engineering
2. Understanding of digital and mixed signal design
3. Familiar with design/simulation/verification tools


More information about NXP in Greater China...

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NXP Semiconductors
NXP Semiconductors

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