NVIDIA

Senior SOC Design Engineer - Switch Silicon

Bengaluru, India
Assembly Perl Python
Description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

The Networking Chip Design team in India is a new team which is growing at a fast pace.

What you'll be doing:

  • You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework
  • Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
  • Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution.
  • Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.
  • Have good grasp of Perl, Python, or other industry-standard scripting languages.

What we need to see:

  • BS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoC’s.
  • Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.
  • Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
  • C/C++ programming or python or any other industry-standard scripting language experience desirable.
  • Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.
  • Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.
  • Excellent verbal and written communication skills to interact with cross functional teams to build consensus.
  • Good teamwork spirit and collaboration skills with team members.
  • Experience in synthesis, physical design and DFT is a plus.
  • Experience in RTL Build and Design Automation is a plus.

Ways to Stand out from the crowd:

  • Experience in RTL coding and debug, as well as performance/power/area analysis and trade-offs
  • Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
  • SOC bring-up and post silicon validation experience
  • Prior experience of smartNIC and/or high-speed interconnects.
  • Strong coding skills in Perl, Python, or other industry-standard scripting languages.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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