Senior Mask Design Engineer - Hardware

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. We would love to hear from you!

We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and multifaceted group of individuals responsible for handling groundbreaking high-speed mixed-signal circuit designs. This position offers the opportunity to have real impact in an innovative, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you'll be doing:

• Lead and implement IC physical layout for mixed-signal functions like high speed SerDes, Analog to Digital & Digital to Analog converters, Bandgaps, Regulators, References, Amplifiers, and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using Cadence tools.

• You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

• Take part in floor planning, custom layout and verifying against design rules and schematics.

• Optimize circuit layouts to meet the specifications for system performance.

• Work with design engineers by providing detailed floor plan and mentorship for matching and high-speed routings.

• Provide support for post-silicon bring-up and debugging.

What we need to see:

• You will have a BSEE (or equivalent experience)

• Minimum of 6 years of mask design / layout experience

• Detailed knowledge of EDA tools from Cadence, Mentor and Synopsys.

• Experience with floor planning, block level routing and large macro level assembly.

• Backgro in running, debugging and ability to customize DRC and LVS decks such as Dracula, Hercules, Calibre.

• Deep understanding of analog circuit layout concepts in submicron CMOS technologies.

• Experience with analog layout for silicon chips in mass production.

• Knowledge of high performance analog and high speed IO layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.

• Proficient in scripting languages like perl, python, skill etc.

• You are able to work effectively in a team, good social skills, excellent interpersonal skills (written and verbal) and brings passion and positive energy.