NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

Location: China, Shanghai

Time Type: Full time

Job Description

By submitting your resume, you’re expressing interest in one of our 2027 Hardware ASIC Engineer New College Grad roles. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience fits one of our new college graduate opportunities. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society — from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.

We offer an excellent opportunity to expand your career and get hands on experience with one of our industry leading Hardware teams. We’re seeking strategic, ambitious, hard-working, and creative individuals who are passionate about helping us tackle challenges no one else can solve.

Potential NCG opportunities in this field include:  

• IP and SoC Level Design and Verification (including multimedia IP) 

• Custom SoC Design and Verification 

• Networking Chip Design and Verification 

• Architectural Power and Energy-Efficiency Modeling 

• DFT 

• Formal Verification 

• Post-Silicon Validation 

What we need to see:  

• Expected to graduate in 2027 with a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field 

• Course or internship experience related to the following areas could be required:

Digital Systems, Digital Design, VLSI Design, RTL Design, Chip Blueprint, Power and Performance Optimization, Testbench Creation

Computer Architecture, Computer Arithmetic, Object-Oriented Programming, CMOS Transistors, Circuits, Infrastructure Development

Architectural Tradeoff Analysis, Power and Noise Analysis, Silicon Instrumentation and Measurement

CAD and Physical Design Methodologies (Flow and Tools Development), Chop Floorplan, Power/Clock Distribution, Packaging, P&R and Timing Closure

Performance, Verification, and Emulation Methodology

Familiarity with hardware verification methodologies, particularly UVM (Universal Verification Methodology), and a working knowledge of formal verification tools. 

Fundamental knowledge of hardware and board-level design, such as power integrity (PI), signal integrity (SI), and PCB-level design.