Serbia-Verification Intern

Location: Serbia (RS)

Description

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research. 

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. 
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. 
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for an enthusiastic, curious, and motivated Design Verification Intern to join our hardware engineering team. The verification team is responsible for ensuring the flawless functionality of our next-generation ASIC/SoC designs before tapeout. In this hands-on learning role, you will be mentored by industry experts, gain real-world exposure to cutting-edge chip design cycles, and tackle foundational verification challenges while contributing to real products.

Requirements

• Currently pursuing a B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field (preferably in your last year of study).
• Strong grasp of digital logic design fundamentals and computer architecture. Basic programming skills in C/C++ or Python. Familiarity with Hardware Description Languages (Verilog, VHDL, or SystemVerilog) through university courses.
• Exposure to basic verification concepts, testbenches, UVM methodology, logic simulation tools, or FPGA design: an advantage.
• Fluent in written and spoken English. 
• Must be available to commit to a full-time schedule for the duration of the internship program.
• Highly inquisitive with a strong problem-solving mindset, eager to learn and absorb new information, an excellent team player, and not afraid to ask questions.

Responsibilities

• Learn and apply industry-standard verification methodologies (such as SystemVerilog and UVM) through guided mentorship and hands-on tasks.
• Assist in writing, compiling, and executing directed and random test cases for block-level RTL designs.
• Help analyze simulation results and collaborate with senior engineers to debug basic RTL or testbench issues.
• Write and maintain utility scripts (using Python, Bash, or Perl) to help automate and streamline daily verification flows.
• Participate in team meetings, verification plan reviews, and document your learning progress, concluding with a presentation of your internship project to the team.