Serbia- Junior Logic Design Engineer

Location: Serbia (RS)

Description

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for a talented junior design engineer to join our silicon design team. The ideal candidate will be eager to learn cutting-edge ASIC design technology and modern ASIC design flows. Candidates will have the unique opportunity to get full support and education from our highly experienced ASIC design team in Belgrade — a team that now holds end-to-end ownership of complete chip development for the HPC/AI market. This is a rare chance to be part of a chip development journey from the ground up, gaining hands-on experience across all phases — from IP and subsystem development, through full-chip design, all the way to system-level understanding — with guidance from a team of engineers with decades of combined ASIC experience every step of the way. Come join Nextsilicon's center of excellence, contribute to one of the most exciting product areas in the industry, and have a big impact on our future products.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience
• 1-4 years experience in logic design and RTL coding in Verilog / SystemVerilog (ASIC or FPGA). Candidates with strong academic accomplishments could also be considered even with less experience.
• Must be familiar with ASIC design and verification processes, methodology and tools.
• Hands-on RTL design experience in SystemVerilog or VHDL
• Solid understanding of synchronous digital design principles: clock domains, reset strategies, timing closure
• Familiarity with simulation and waveform debugging (e.g. VCS, Questa, ModelSim)
• A background in computer architecture, multi-core architecture, cache coherency, high speed memory subsystems or high speed interconnects is nice to have.
• Strong analytical and problem-solving skills with attention to detail
• Good communication skills; ability to work effectively in a collaborative, cross-functional team

Responsibilities

• Design, Implement and Integrate design blocks/IPs and complex design subsystems in SystemVerilog based on micro-architecture specifications.
• Participate in the adoption of the AI methodologies in the digital design practice and design flow
• Participate in design reviews, providing and incorporating constructive feedback
• Debug RTL issues identified during block-level and system-level simulation
• Collaborate with verification engineers to achieve functional coverage closure
• Support physical implementation handoff (timing constraints, CDC checks)
• Maintain up-to-date design documentation and contribute to micro-architecture specifications
• Work closely with senior engineers to continuously develop technical expertise in high-performance hardware design