India-DFT Engineer

Location: India (IN)

Description

NextSilicon is reimagining high-performance computing. Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research. 

At NextSilicon, everything we do is guided by three core values:

• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. 
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. 
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

At NextSilicon, we are reimagining high-performance computing. Our pioneering coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC to fulfill its promise of breakthroughs in all fields of advanced research.

NextSilicon is looking for a talented and experienced DFT engineer to play a crucial role in the DFT implementation of the company’s next SOC. A Design for Test (DFT) Engineer plays a critical role in the semiconductor and electronics industries, focusing on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. The primary goal of a DFT Engineer is to integrate test structures within the design of electronic components to facilitate efficient testing throughout the lifecycle of the product, from production to deployment and maintenance.

Requirements

• 8+ years of experience in DFT methodology and implementation is a must
• Strong understanding of digital design and test principles.
• Proficiency in DFT techniques, such as Scan compression, SSN, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
• Experience with EDA tools (e.g., Synopsys FusionCompiler, TestMax, Mentor Tessent) and scripting languages (e.g., Python, TCL, Makefile, etc).
• Knowledge of IC design flows, verification tools, SDC, fault models.
• Ability to identify, analyze, and resolve testing challenges.
• Work effectively within multidisciplinary teams, communicating complex technical details clearly.
• Proven success in development of complex custom ASIC products in advanced process nodes.
• Hands-on experienced and successful taped out several ASICs.
• Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goal.

Responsibilities

• Define DFT Architecture and Methodologies for the next generation SoCs.
• Perform scan, MBIST, Boundary scan insertion and ensure architectural spec is met.
• Develop high quality tests to verify DFT functionality in RTL and gate level (no-timing and timing) simulations.
• Analyze fault models and optimize for high coverage (stuck-at, transition, path delay, IDDQ, etc).
• Working closely with cross functional teams to develop and verify DFT’s structures and constraints.
• Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.