Senior Physical Design Engineer

Microsoft’s Cloud Compute Development Organization (CCDO) is seeking passionate, driven and intellectually curious engineers to join our silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, custom IP and SOC designs that can perform complex and high-performance functions in the most efficient manner. This team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems.

#SCHIEINDIA

Required:

• BS/MS in Electrical or Computer Engineering
• 10+ years of experience in semiconductor design.
• Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

 Preffered:

• Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes.
• Excellent project management skills and ability to juggle multiple projects at once.
• Strong understanding of constraints generation, STA, timing optimization, and timing closure.
• In-depth understanding of design tradeoffs for power, performance, and area.
• Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
• Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Fusion Compiler, Innovus etc.
• Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise.
• Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus
• Strong problem-solving and data analysis skills
• Automation skills using scripting languages such as Perl, TCL, or Python.

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

In this high impact role on the team, you will be responsible to: 

• Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
• Own complete PD execution of Sub-systems/Sub-chips instantiating multiple other Physical partitions.
• Own partition floorplanning for optimizing blocks for Power, Performance and Area.
• Have close collaboration with RTL team to help drive and resolve design issues related to block closure.
• Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Implement robust clock distribution solutions using appropriate methods that meet design requirements.
• Make good independent technical trade-offs between power, area, and timing (PPA).
• Be able to guide and coordinate with all sub-partitions PD to be able to take the Sub-chip through PD (construction through signoff) closure.
• Additionally flow flush PD TFM on few design partitions for early identification of any design PD flow issues before every PD TFM release is proliferated and deployed across all partitions/subchips for PD execution.
• Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate).