Senior Logic Design Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.  

We are looking for a  Senior Logic Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a self-starter who will thrive in this cutting-edge technical environment.  

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 4+ years expertise in high-speed digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure
• 4+ years of experience in synthesis, floorplanning, timing constraints, power / performance / area (PPA) trade-offs, and post-silicon debug
• Experience in one or more of the following:
  • High-performance memory subsystems and multi-level caches
  • System knowledge (software/firmware/hardware interactions and optimization)
  • High-throughput processor design
  • Industry-standard bus interfaces such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocols
  • Fixed and floating-point arithmetic datapath design and optimization
  • Fabric and interconnect

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements is required for this role. These requirements include but are not limited to the Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications: 

• 10+ years of industry experience in logic design delivering complex solutions. 

• Successful Application-Specific Integrated Circuit(ASIC) tape outs in deep sub-micron technologies. 

• Scripting language such as Python or Perl. 

• Good background in debugging designs as well as simulation environment. 

• Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage. 

• Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs. 

• Working knowledge of writing assertions, coverage, and formal verification. 

• Effective communication skills, self-motivation, and ability to collaborate with larger teams within Microsoft. 

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay   

Microsoft will accept applications for the role until October 22, 2024.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

• Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features. 
• Be responsible for 
  • Logic design/Register Transfer Level (RTL) entry 
  • Design quality, including: Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc. 
  • Timing closure of high-performance digital Intellectual Property (IP) 
  • Silicon validation 

• Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.
• Interface with architecture, physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design.
• Provide technical leadership through mentorship and teamwork. 
• Other
  • Embody our Culture and Values