Senior IP RTL Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior IP RTL Design Engineer to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Computer Development Organization (CCDO) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Senior IP RTL Design Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Experience in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Experience with Industry standard interface protocols such as Advanced eXtensible Interface(AXI), Advanced Peripheral Bus(APB), Coherent Hub Interface(CHI) etc.
• Experience with Advanced RISC Machines(ARM) Fabric Intellectual Property(IPs).
• Experience with IPXACT.
• Understanding of Computer Architecture fundamentals.
• Ability to write scripts using Python, Tcl, Perl etc.
• Experience in Electronic Design Automation(EDA) tools such as Verilog Compile Simulator(VCS), Verification Compiler Low Power(VCLP), Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
• Proficiency with UPF (Low power intent).
• Proficiency in clock crossing techniques.
• Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
• Applied understanding of low power design principles. 
• Understanding in design closure challenges in power and clock domain crossings.
• Experience writing timing constraints, exceptions, and clock constraints; good understanding in Synopsys Design Constraints(SDC) commands and Tool Command Language(TCL) constraints.
• Organized and Detail oriented.
• Good verbal and written communication skills.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay   

Microsoft will accept applications for the role until December 18, 2024.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

#azurehwjobs

• Own subsystem integrating several industry standard IPs.
• Specifying and micro-architecting digital blocks, and performing concept studies to guide performance, power, and gate count.
• Write Register Transfer Level(RTL) code for blocks based on architectural specifications.
• Participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team.
• Assess and then refine the implementation for area, power, and performance.
• Define, create, and maintain project documentation, including design documents with analysis reports.
• Collaborate with architecture, subsystem owners, and IP providers to configure the IP to maximize performance for various use cases.
• Grow your micro-architectural knowledge of your own blocks as well as other blocks in the System on Chip(SoC).
• Describe the power intent of the design through Unified Power Format(UPF).
• Perform design quality checks such as Lint, Clock Domain Crossing(CDC), Reset Domain Crossing(RDC), Low Power Intent, Synthesis, Logic Equivalence.
• Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.
• Automate tasks using scripting for efficiency.
• Delight your customers who receive your deliverable by providing high quality functional block on schedule and with professional integrity.
• Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies.
• Challenge the status quo with a growth mindset.
• Other
  • Embody our Culture and Values