Senior Engineer, Debug Logic

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. 

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CCDO org is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.  

We are looking for a Senior DFD (Design for Debug) Engineer to join the team. 

• Experience in designing debug/diagnostics logic. Includes building and integrating any of the Debug IPs such as the ones provided by ARM Coresight. 

• Highly Proficient in Verilog/System Verilog coding constructs & good with scripting using Python etc. 

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) 

• Strong understanding in clock crossing techniques & UPF (Low power intent). 

• Previous experience working on post-silicon debug / validation. 

• Familiarity with Industry standard interface protocols is a plus. 

• Familiarity with Synthesis and STA tools is a plus. 

• Good verbal and written communication skills. 

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

In this high impact role on the team, your responsibilities will include: 

• Define the micro-architectural implementation spec for debug blocks/fabrics & implement the micro-architectural specification in Verilog or System Verilog. 

• Assess and then refine the implementation for debug coverage, area, power and performance. Ensure quality with checks covering Lint, CDC, Low Power intent and more. 

• Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. 

• Collaborate with highly energetic cross functional team members (system architects, front-end & back-end design verification, and post-si validation folks) with respect and with One Microsoft mentality to establish synergies. 

• Delight your customers by delivering cutting-edge debug infrastructure for custom SoC designs that can perform complex and high-performance functions. Challenge the status quo with growth mindset.