Principal Analog Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. 

The Microsoft Silicon Team is continuing to revolutionize consumer electronic devices & Cloud Computing.  We are looking for an experienced Principal Analog Design Engineer who is innovative and has a passion for analog design and verification of next generation Consumer & Cloud Computing Devices.  

The SCIPS Analog group designs high performance mixed signal ASICs in leading edge CMOS technology using custom IC design tools. You will work in a diverse, dynamic environment and interact with other teams to help design and test great products! 

The ideal candidate is a self-starter, highly motivated engineer with excellent technical & interpersonal skills, used to working independently or as a key member of a fast-moving design team. 

#azurehwjobs  

• You should have a BSEE or equivalent, MSEE/PhD preferred. 

• You should have at least 10-15 years of Analog & Mixed Signal IC circuit design delivery of medium-large complexity designs.  You must have 5 plus years of Lead experience, including day-to-day task coordination and overall delivery responsibilities. 

• You have delivered Analog IP’s successfully in mass production in FinFET processes. 

• You have a proven track record at each of the following stages in product development: 

• Experience in leading high-speed and low-power RX/TX/Clocking designs, High-Speed SerDes or D2D interconnect designs, or large blocks such as PLLs, Power Regulators, Data Converters, etc. 

• Design partitioning, power/jitter budgeting and timing analysis.  Knowledge of lower power design techniques, calibration, parasitic extraction, EM/IR/ESD & Signal Integrity Design. 

• Detailed design and mixed signal simulatiins of analog/mixed signal building blocks and one or more of the following subsystems: ADC, DAC, PLL, clocking systems, sampler, RX front-end, TX driver, serializer, de-serializer, voltage regulator, bandgap, bias circuits. 

• You have detailed knowledge of EDA tools for Cadence, Mentor, Synopsys for Analog Design. 

• You are a self-starter with the ability to define and adhere to a schedule. 

• You have good inter-personal skills, you are able to interface with a variety of external partners (customers, architects, designers, project managers, etc.) and are able to deliver complete layouts to customers. 

Ability to meet Microsoft, customer and/or government security screening requirements may be required for this role. These requirements may include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.  
 

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

#ahsi  #SHPE24MSFT  #SCHIE #SCHIEINDIA

• The primary responsibility of this position is to lead Architecture-to-GDS delivery of cutting edge, high-performance, high-speed, low-power Analog IP designs for interconnectivity solutions and fundamental Analog circuit blocks for various Microsoft products in various process nodes including deep FinFet, following industry best practices.  You will technically lead a design team that will produce schematics, verify in simulation, and work with mask layout teams to deliver a final IP GDS. 
• You will coordinate tasks with junior members of the team, develop plans for Analog IP execution, follow processes/methodologies to deliver IP blocks.  You are a very hands-on contributor yourself. 
• You will manage on-boarding/offboarding of additional external contingent staff to supplement existing team for overflow. 
• You are proficient in Analog and Mixed signal IC circuit designs, design validation simulations (pre and post-layout), follow checklists/presentation templates, supervise floor-planning and monitor layout progress.  You will coordinate bench validation of IP in Silicon, and IP characterization on bench and tester.  You will establish flows/methodologies/processes for execution along with peers. 
• You will work along with other members of the team to deliver IP’s, including project planning, schedule tracking, report generation.  You will follow / augment / put-in-place processes/methodologies in place for high quality execution along with peers.