For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.

Role and Responsibilities

• Responsible for Design and development of critical Design and Co-optimization objectives, mixed-signal, custom digital block and full chip level integration support.

• Build and tapeout PWF Reticles Design

• Engage with Scribe Design team to capture Advanced Packaging requirements and Review

• TSV design engagement with HIG-HBM DTPCO teams (electrical , thermal and mechanical performance)

• Creation and Maintenance of DFMEA related to advanced packaging process steps like PWF, die stacking etc

• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design

• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.

• Responsible for on-time delivery of block-level layouts with acceptable quality.

• Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.

• Guide junior team-members in their execution of Sub block-level layouts & review their work

•  Contribute to effective project-management.

• Effectively communicating with Global engineering teams to assure the success of layout project.

Qualification/Requirements

• 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )

• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.

• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,

• Should have hands on experience in Reticle development and Full CHip Verification.

• Should have hands on capability to automate or use AI features for fast and efficient project execution

• Good understanding of Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)

• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,

• Excellent command and problem-solving skills in physical verification of custom layout.

• Multiple Tape out support experience will be an added advantage.

• Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development.

• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.