As a Sr Design Engineer, you will work on design, simulation, and validation of next‑generation High‑Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co‑optimization with GPUs/accelerators. 
This role sits at the intersection of DRAM design and high‑performance computing, enabling future AI/ML, HPC, and advanced graphics products. 

 
In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. 

Responsibilities will include, but are not limited to: 

• Design, optimize, and valSupport post‑silicon bring‑up, failure analysis, and design correlation when required 

• Work closely with layout engineers on floorplanning, placement, routing, and design rule compliance  

• Review parasitics, EM/IR, and reliability results; drive design or layout fixes as needed  

• Ensure designs are manufacturable and meet foundry and packaging  

• Minimum Qualifications: 

• Prior experience in HBM, DRAM, high‑speed I/O, or memory‑related designs  

• Familiarity wiconstraints 

• Apply AI/ML- 

• nabled tools that enhance productivity, design quality, verification coverage, and time-to-market 

• th 3D‑stacked architectures, TSVs, wide I/O interfaces, or PHY‑adjacent logic 

• Understanding of DRAM array control and high speed circuit design 

• Experience in function verification and timing analysis with mixed signal design. 

• Familiar with device reliability. Experienced in reliability mitigation technology and verification flow. 

• Familiar with analog/digital simulation tools, i.e., HSPICE, VerilogHDL, Primesim’ 

• MS in Computer Engineering or related field 

• 3 years DRAM Design or Verification experience. 

• Excellent Problem‑Solving & Analytical Skills 

• idate memory, logic, analog, or mixed‑signal circuits used in HBM products, including PHY‑adjacent or subsystem logic 

• Contribute to HBM architecture definition, block‑level specifications, and design tradeoff analysis across performance, power, area, and reliability  

• Perform pre‑layout and post‑layout simulation, modeling, and analysis to ensure robust design margins  

• Support tape‑out activities, ECOs, and reticle experiments as required 

• Participate in functional, timing, and power verification using industry‑standard simulation tools  

• Collaborate closely with Design Verification teams to review test plans, debug failures, and close coverage gaps  

(LLM)