Senior Engineer II - Verification

Location: India - Bangalore

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

As a Senior PCIe Verification Engineer, you will work on verification environments for our next-generation Data Center Storage products, including enterprise-class PCIe Gen5/6/7 memory controllers and other PCIe/CXL-based SoC products. You will drive verification efforts with a strong focus on PCIE/CXL protocol behavior, ensuring robust, silicon-ready designs. These complex SoC silicon devices enable top-tier data centers across Next-Gen Storage, Artificial Intelligence, and High-Performance Computing market segments.

Job Responsibilities

• Define verification plans and build testbenches using UVM/System Verilog for PCIe Gen5/6/7 IP.
• Interpret PCIe protocol specifications to develop and execute verification plans in simulation environments.
• Integrate and configure third-party PCIe Verification IPs (e.g., Synopsys, Cadence) for Gen5/6/7 verification.
• Develop test cases, checkers, and functional/code coverage models per the verification plan.
• Collaborate with firmware, emulation, and silicon validation teams; support pre-silicon and post-silicon bring-up/debug.

Requirements/Qualifications:

• Bachelor's/master’s degree in Electronics/VLSI Engineering with 6+ years of RTL verification experience, including 2+ years specifically in PCIe protocol verification.
• Strong hands-on expertise in UVM/System Verilog-based testbench development
• Domain expertise in PCIe Gen5/6/7 protocols, focusing on Transaction Layer verification.
• Expertise in verifying PCIe features, including compliance verification on PCIe/CXL EP/RC.
• Knowledge of AMBA AXI/AHB/APB protocols.
• Expertise in test plan creation, testbench architecture, and test scenario development, including functional coverage and code coverage management.
• Strong analytical and problem-solving skills, with a proven ability to work independently.
• Excellent written and verbal communication and documentation skills.

Travel Time:

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