Senior Engineer I – Verification

Location: India - Chennai

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

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Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Job Summary

We are seeking a highly skilled Senior Engineer I – Verification with a strong understanding of full-chip verification and exposure to AMS (Analog/Mixed-Signal) environments. This role focuses on ensuring functional correctness and quality of complex SoC designs by developing and executing robust verification strategies across digital and mixed-signal domains.

Key Responsibilities

• Lead and contribute to full-chip verification for complex SoC and mixed-signal designs
• Develop and execute verification plans, testbenches, and methodologies using SystemVerilog and UVM
• Collaborate with AMS, digital design, and architecture teams to validate mixed-signal behavior
• Integrate and verify analog IP interactions within full-chip and subsystem environments
• Drive coverage closure (functional, code, and assertions) at block, subsystem, and full-chip levels
• Debug and resolve complex failures involving digital, analog, and interface interactions
• Support power-aware, reset, and clock-domain verification
• Mentor junior engineers and promote verification best practices
• AI- Skills
  • Leverage AI/ML tools to improve RTL development, verification productivity, and debug efficiency.
  • Use and prompt LLM based  assistants to generate code, stimuli, documentation, root cause analysis and scripting
  • Apply AI driven techniques for log analysis, waveform triage and failure clustering
  • Ability to design, run, and analyze AI‑assisted trials/experiments to improve productivity or quality
  • Know-how of integrating AI tools with existing EDA flows and scripts.

Requirements/Qualifications:

• Bachelor’s or Master’s degree in Electronics Engineering or related field
• 5+ years of experience in ASIC/SoC verification
• Strong expertise in SystemVerilog and C based coding for verification
• Solid understanding of full-chip SoC architecture and integration
• Exposure to AMS verification concepts, including interaction between analog and digital domains
• Experience with simulation, debugging, and coverage analysis tools
• Proficiency in scripting languages such as Python, Perl, or Shell
• Strong analytical, debugging, and communication skills

Preferred Qualifications

• Hands-on experience with AMS simulators or mixed-signal verification flows
• Familiarity with real-number modeling (RNM) or behavioral modeling of analog blocks
• Experience with low-power verification and power-aware simulations
• Knowledge of formal verification methodologies
• Experience verifying interfaces such as PLLs, ADCs/DACs, or power management blocks
• Prior mentoring or technical leadership experience

Travel Time:

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