Senior Engineer I - Design

Location: India - Hyderabad

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

• The design off ASIC blocks to be used within the next generation Microchip FPGA devices. These devices contain RiscV CPUs and all the associated functions to create true SOC functionality. It is expected that the successful candidate will be able to customize and integrate third-party IP blocks, and to create new ASIC blocks as required for the SOC and integration, involved from architecture through to production release. Integration also involves the design of compiled memories and integrating within the SOC along with memory MBIST.  The candidate must be familiar with Verilog/System Verilog coding and standard Synthesis and STA tools.
• The position will involve interaction with cross geography teams and cross functional teams like DFT and PnR and logic verification.

Skills:

• Experience in block level micro-architecture and RTL design of complex ASIC blocks.
• Experience in IP development from Scratch and integration into SOC.
• Experiencing in digital flows like linting, cdc, synthesis, STA.
• Experienced in Verilog/ System Verilog coding, assertions and unit level verification.
• Good understanding of microprocessors and on-chip bus Structures (AXI, AMBA, peripheral interconnects and communication protocols)
• Experience is PCIe / USB is a plus point.
• Deep understanding least three of
• RiscV or ARM CPUs
• Network On Chip Bus Interconnect (added plus point)
• Ethernet
• PCIe / USB
• SD/MMC
• DDR/LPDDR
• High speed serial interfaces
• IO, mixed signal designs
• gearing logic

Requirements/Qualifications:

• 6-7 years of professional experience in RTL design, linting, cdc, synthesis, STA
• Bachelor with Diploma in VLSI / Master of Engineering / Engineering Degree with experience in VLSI

Travel Time:

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