Senior Engineer I Design

Location: India - Chennai

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

DFT Engineer

We are looking for a skilled and motivated DFT Engineer with 5+ years of experience in VLSI design. The candidate will be responsible for handling DFT activities (Boundary scan, Memory BIST and scan insertion, ATPG, gate-level simulations and Silicon Bring up and failure debug on ATE) across complex SoC/IP designs and will work closely with RTL and STA teams to ensure high-performance and power-efficient silicon implementation.

Key Responsibilities:

• Perform block-level and full-chip DFT activities for ASIC/SoC designs.
• Boundary scan insertion, Memory BIST insertions and Scan insertions with compression logic
• Understanding and fixing the DFT DRCs rules
• ATPG (stuck-at , transition and Iddq mode)
• Patterns verification with timing and debug DFT issues across RTL/Gate-level stages
• Collaborate with ATE teat to support first silicon bring-up , failure analysis

Required Qualifications:

• Bachelor’s or master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 5+ years of hands-on experience in Design For Testability for ASIC/SoC designs.
• Strong understanding of digital design fundamentals and timing concepts.
• Experience with industry-standard DFT tools such as Siemens, Cadence and Synopsys
• Good knowledge on DFT DCR rules
• Familiarity with scripting languages such as Tcl, Perl, or Python.
• Strong analytical, communication, and teamwork skills.

Requirements/Qualifications:

Bachelors Degree in Electronics Engineering.

Travel Time:

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