Principal Engineer-Physical Design

Location: India - Bangalore

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip AES Design team in Bangalore is looking for an experienced and motivated Physical Design Principal Engineer to implement RTL2GDSII for larger SOCs. As a member of Physical Design team, you will be responsible for place and route, timing closure and physical verification checks for multiple blocks and top level. The candidate should have experience with Physical Design tools. The candidate should have in depth knowledge of Innovus/ICC2 tool execution.

Location: Bangalore, India

Job Responsibilities:

The employee is responsible for complete physical design of multiple large complex sub-systems & Top-level implementation in low node technologies like 16nm & 3nm. The employee is expected to take ownership of Full Chip/multiple complex design & flow challenges, which would include:

• Floor-planning, Place & Route and CTS using physical design tools like Innovus and ICC2.
• Physical verification and IP Integration
• Physical Design Flow and Methodology.
• IR and EM checks.
• Ability to lead the team along with the project execution.
• Use metric-driven techniques to help ensure first-pass working silicon.
• Communicate regularly with the implementation and project team to resolve issues, and communicate status to leads
• Occasional travel needed.
• Mentor and guide junior physical design engineers, providing technical leadership and best practices.

Requirements/Qualifications:

Job Qualifications:

This position requires at least B.E/B.Tech/M.Tech in Electronics with 10+ years of Physical Design experience in a fast-paced environment with following experience.

• Expertise in Physical Design activities: Floor-planning, CTS, P&R, Extraction, Power IR/EM, Physical Verification (DRC/LVS) and Signal Integrity
• Advanced knowledge of place and route methodologies and low power methodologies.
• Static Timing/Crosstalk Analysis and timing closure
• Must have an understanding of Synthesis/DFT concepts and flow.
• Experience in working with analog IP, hard and soft macros and delivering hierarchical design projects
• Expertise with Backend Tools (Innovus or ICC2, Calibre or PVS, PrimeTime or Tempus, Redhawk or Voltus, Starrcxt or QRC)
• Strong programming knowledge in Perl, TCL, and/or Shell and Python Scripting
• Excellent oral and written communications skills in order to work with teams across the globe
• Must have led subsystems or junior team members technically.

Travel Time:

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