Engineer II - Test

Location: India - Hyderabad

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

•                You will work in Test Development team from Hyderabad to develop and deploy tests on real silicon.

•                These tests are intended to catch manufacture defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, Logic Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to deploy tests in ATE/Tester setup, cross-porting failures in full chip logic verification Vs bench Vs ATE.

•                You will work closely with Silicon design engineers, Verification engineers Process engineers, Yield enhancement engineers and test engineers to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required.

•                Responsibilities:

•                Develop and debug test programs on J750 ATE test platform

•                Develop test firmware and Generate test vectors

•                Develop ATE tests  using VBA, C/C++, and java codes

•                Generate test programs using make script

•                Support New Product Development objectives through Silicon Validation.

•                Support improvement projects to reduce test cost in manufacturing. 

•                Maintain, develop, and implement bench test methodologies on new devices.

•                Participate as a member of the development team.

•                Support Yield issues, Failure Analysis and help with silicon debug and ramp up

•                Test specification, plan, and documentation

Requirements/Qualifications:

•                1 - 3years’ experience on ATE tester preferably on J750 tester

•                B-tech or M-tech in Electronics Engineering or Electrical Engineering

•                Hands on experience in testing and debug of silicon (such as FPGA, ASIC, test chips, etc.)

•                Good programming skill: C, C++/Java with exceptionally good expertise at low level          C/assembly

•                Firmware Development: Any micro-controller / ARM

•                Understanding basics of silicon manufacturing issues and their design methods

•                MBIST, Scan Methods and related yield issues

•                Hands-on experience with Verilog and/or VHDL o Behavioral, RTL and Gate Level coding, Programming Language Interface

•                Exposure to ASIC/FPGA design flow and methodology is a plus o HDL, synthesis, static timing analysis, constraining, Place & Route

•                Hands on experience on Silicon Debug, exposure to JTAG based debuggers is a big plus

•                Comfortable with Unix, Fluent in Perl and/or Shell scripting, agile with Make, and familiar with Revision Control (CVS, SVN, …)

•                Excellent communication, documentation and presentation skills.

•                Must have strong self-learning ability, leadership, and enjoy working in teams

•                Familiar with schematic design and PCB layout.

•                 Knowledge of FPGA architecture is a plus

•                Hands on knowledge of basic lab equipment such as oscilloscope, multi-meters, logic analyzer, etc.

•                Excellent analytical and debugging skills and the ability to proactively solve issues.

•                Excellent interpersonal and teamwork skills

Travel Time:

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