Engineer I - Software (FPGA Timing and Power)

Location: CA - San Jose - 3850 N. First St

Time Type: Full time

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

The Microchip FPGA Software Engineering team delivers a comprehensive software suite for designing Microchip’s FPGAs and managing the entire design flow from entry, to synthesis, through place-and-route, timing, power analysis, and simulation. Within the Software organization, the Timing, Power, and Modeling group is responsible for developing high-quality and user friendly software for the evaluation of FPGA design performance, both for speed and power consumption. These are key sign-off tools, distributed along with the hardware to a wide range of customers and are also used internally for the exploration of new FPGA architectures.

We research and implement cutting-edge fast and scalable algorithms with the objective of helping FPGA designers close on their timing requirements within an increasingly limited power budget. To meet these goals, we draw from a variety of computer science domains, including: numerical optimization, linear programming, graph theory, modeling non-linear electronic components, large data processing and machine learning based regression and classification methods.

As a member of this R&D team, you will leverage your solid foundations in computer science to develop next generation performance evaluation (timing and power) algorithms. Your work will used by thousands of well-known customers, and your achievements will improve the overall solution, both internally and externally.

Primary Job Responsibilities:

• Develop solutions tailored towards supporting very large graph representation.
• Improve tools' run time to competitive levels.
• Improve the user experience through guidance tools and context-based help.

Secondary Job Responsibilities:

• Integrate some of the capabilities in an internal flow to evaluate future FPGA architectures.
• Participate to the R&D exploration activities on advanced topics such as OCV, SSTA, IR Drop
• Help with the enforcement of Microchip’s Software Development Processes
• Perform design reviews, unit testing, and code reviews
• Own and sustain product features and provide customer support
• Continue learning latest EDA discoveries and contribute to the team discussions

Requirements/Qualifications:

Minimum Qualifications:

• BS in CS/EE or related field
• Strong knowledge in C++, as well as a deep understanding of algorithms and data structures
• Experience with shell scripting languages (Perl, Python, Bash, TCL)
• Excellent problem-solving skills and attention to detail
• Strong communication skills and the ability to work collaboratively across teams

Preferred Qualifications:

• Experience with source code management systems (ClearCase, Git, SVN, Perforce)
• Exposure to parallel programming techniques, like TBB
• Familiarity/knowledge/experience with any of the following would be a plus: FPGA architectures, Qt, AI-based applications

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

70% sitting, 15% standing and 15% walking, 100% indoors; Usual business hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in the US, is $70,304 - $143,000.*

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.