- Perform in-depth power and performance profiling of ML models and ML benchmarks on ML accelerators.
- Examine the power and performance characteristics of ML accelerators in relation to various types of ML models.
- Develop an optimal mapping definition for ML models to ML accelerators.
- Identify power and performance bottlenecks and optimization opportunities in ML models, ML accelerators, and system architectures.
- Collaborate with cross-functional teams to prototype and productize optimizations.
- Conduct power and performance analysis of end-to-end AI powered use cases, identify power optimization opportunities in software, firmware and overall system architecture.
- Work alongside system architects to create a roadmap for the next generation of ML accelerators and wearable system architecture.
- Currently has, or is in the process of obtaining a Master’s degree in Computer Science, or Computer Engineering with a focus on ML.
- Proficient in ML frameworks such as PyTorch or TensorFlow.
- Familiarity with edge ML frameworks like TensorFlow Lite or similar technologies.
- Experienced with edge ML accelerator compiler toolchains, including ARM Vela or others.
- Experience in embedded software development using C/C++.
- Strong understanding of computer architecture.
- Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment.
- Currently holds or is pursuing a PhD in Computer Science or Computer Engineering with a focus on ML.
- Experience in developing and optimizing ML models for edge devices.
- Familiarity with ML accelerators and their internal architecture.
- Knowledge of ML model optimization techniques, such as quantization and pruning.
- Experience with profiling ML model execution on and off-device.
- Familiarity with power optimization techniques, such as DVFS, power and clock gating.
- Intent to return to degree-program after the completion of the internship.
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