- Contribute to our developer infrastructure, including simulation and HW emulation platforms, to enable performance measurement and optimization for Meta’s in-house accelerator programs.
- Understand and contribute to the collective communications library, intended to be deployed on Meta’s AI/ML superclusters.
- Support networking and compute hardware acceleration techniques to improve ML inference and training model performance.
- Perform architectural analysis to ensure system designs meet performance, scalability, and reliability requirements.
- Implement simulation models for Meta’s Accelerator ASICs, develop and analyze various scenarios to evaluate data center performance and identify potential improvements.
- Collaborate with architects and engineers to integrate simulation results into system design processes.
- Use instruction set simulators to define performant firmware for Meta's training/inference accelerators.
- Collaborate with hardware and firmware teams to ensure accurate modeling and simulation of accelerator functionalities.
- Analyze simulation results to guide firmware development and optimization efforts.
- Bachelor or higher in Computer Science, Computer Engineering, or any other relevant technical field
- 5+ years experience in developing C++ codebase
- 5+ years experience in developing Python codebase
- Understanding of performance and benchmarking measurement and optimization on collective communications and distributed at-scale model training
- Full-stack experience and understanding of AI/HPC systems, from HW/infrastructure through the application layer, performance optimizations, including familiarity with relevant tools, libraries, and frameworks (e.g., NCCL, PyTorch, CUDA)
- Experience in one or more of the following machine learning/deep learning domains: hardware accelerators, AI Infrastructure, and/or high performance computing (HPC), particularly pertaining to interconnect and collective
- Knowledge of AI/HPC hardware requirements and specifications (e.g., configuring hardware components, GPU, memory, network for AI/HPC workloads)
- Understanding of the transport stack (e.g., RoCE), its constraints and performance measures and how transport considerations enable the collective communications stack
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