- RTL development using SystemVerilog.
- Participate in Micro-architecture, Design, and Verification reviews and provide feedback.
- Analyze design and enhance PPA (Power, Performance, Area).
- Support Verification to analyze and improve Verification Coverage.
- Debug simulations.
- Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
- Knowledge of VHDL, Verilog or SystemVerilog.
- Knowledge of Logic Design Fundamentals.
- Must obtain work authorization in the country of employment at the time of hire, and maintain on-going work authorization during employment.
- Experience with Lint, Synthesis, Timing Closure, Formal Verification or Physical Design tools.
- Experience with scripting languages (Python, Perl, TCL, shell scripting)
- Experience with AR/VR technologies, Compression, Image Processing.
- Experience in data path development.
- Demonstrated experience via an internship, work experience, coding competitions, or widely used contributions in open source repositories (e.g. GitHub).
- Intent to return to degree-program after the completion of the internship/co-op.
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