- Vendor engagement, IP review, and selection for parallel links Guide integration and bring-up of parallel links
- Work closely with ASIC and SI teams to close links using Matlab link simulations
- Explore next-generation interfaces, including PHY, DSP, FEC, and OCI technologies
- Design and develop custom memory regulator architectures
- Bachelor's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
- 10+ years experience with analog design
- Experience with ASIC design and tape-out cycles
- Knowledge of parallel interface protocols (UCIE, BOW, JEDEC) and chip layout background
- Experience working with IC foundries and understanding IP vendor limitations and engagements
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- Experience with parallel interface protocols (UCIE, LPPDR, BOW) and architectures
- Knowledge of OCI (Optical Compute Interconnect) and its application to parallel links
- Experience with parallel link design, simulation, and validation (e.g., Matlab, SPICE) Understanding of signal integrity and power integrity challenges in parallel interfaces
- Experience with chip-package-board co-design and co-validation for parallel links
- PHD or MS in Electrical Engineering or related field
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