Member of Technical Staff, Reliability Engineer

Team: Product R&D Engineering

Location: Redmond, Washington

Commitment: Full Time

Workplace Type: onsite

Job Description:

We are looking for a reliability engineer to own the reliability of the LCM itself — the chip at the core of everything Lumotive ships. The LCM is a new class of semiconductor device combining a CMOS backplane, novel thin-film material stacks, and liquid crystal, and it can fail in ways that go beyond the standard CMOS reliability playbook. This is not a turn-the-crank qualification role: some failure modes are unfamiliar, the acceleration models often have to be built from data we generate ourselves, and the person in this seat is expected to develop a deep, first-principles understanding of how and why LCMs fail.

You will design and run accelerated stress tests, perform hands-on failure analysis, build lifetime models, and correlate reliability outcomes back to wafer fab process splits, materials, and assembly. Just as importantly, you will look ahead for failure modes we have not characterized yet — anticipating how a new device in new use conditions can behave — so the team understands the risks early. Your findings will directly drive process, design, and materials decisions and help accelerate our ramp to high-volume production.

Responsibilities:

Own core LCM reliability at the chip level: define the stress test strategy, execute it, and be the authority on LCM failure modes, mechanisms, and lifetime
Design and run accelerated life tests (HTOL, high temperature storage, temperature cycling, humidity / biased-humidity, optical exposure) and define new stress conditions that surface latent failure modes early
Perform hands-on failure analysis: optical and electrical inspection, defect tracking and precursor identification, root-cause hypothesis generation and testing
Build statistical lifetime models (time-to-failure distributions, acceleration factors, activation energies) to project reliability from accelerated conditions to customer use conditions
Correlate reliability outcomes with wafer fab process splits, materials experiments, and assembly variables; drive design-of-experiments with process and fab partners to improve intrinsic reliability
Define pass / fail criteria, burn-in, and screening strategies to keep early failures out of customer deliveries
Develop and maintain the analysis tooling (Python, test databases, dashboards) that turns raw stress-test data into conclusions
Communicate findings rapidly and clearly: document every study in our knowledge base with conclusions and next steps, present at reliability reviews, and flag new failure modes to the broader team the day you find them

Qualifications:

Bachelor’s degree in electrical engineering, physics, materials science, or related fields is required. A Master’s or PhD is preferred.
Minimum of 5 years of experience in semiconductor or optoelectronic device reliability, failure analysis, or closely related roles is required.
Hands-on experience designing and executing accelerated stress tests (e.g., HTOL, temperature cycling, humidity / HAST, high temperature storage).
Hands-on failure analysis experience: optical microscopy, electrical characterization, and systematic root-cause investigation.
Statistical reliability analysis skills: time-to-failure distributions (e.g., Weibull), acceleration modeling (e.g., Arrhenius), and lifetime projection.
Demonstrated experience characterizing failure modes that fall outside standard textbook models — working them from first principles rather than relying solely on established qual flows.
Proficiency in Python, JMP, or similar for data analysis of large reliability datasets.
Strong written and verbal communication skills; disciplined about documenting work with clear conclusions and next steps.
Intellectual curiosity and ownership: you think about what can fail constantly, and you dig until you understand why.
Background in liquid crystal devices (LCoS, displays), MEMS, image sensors, photonics, or other emerging semiconductor device technologies.
Familiarity with reliability and quality standards (JEDEC, AEC-Q100) and how to adapt them to devices they were not written for.
Experience running split-lot design-of-experiments with wafer fabs or materials vendors to improve reliability.
Experience defining burn-in and production screening for early-failure elimination.
Experience with test data infrastructure: databases, Tableau or similar dashboards, Git and software development best practices.