Staff Power Integrity Engineer (Bay Area and Boston)

Lightmatter builds chips that enable extreme-scale artificial intelligence computing clusters. If you're a collaborative engineer or scientist who has a passion for innovation, solving challenging technical problems and doing impactful work like building the world's first optical computers, consider joining the team at Lightmatter!

We are defining what computers and human beings are capable of by delivering a fundamentally new kind of computer that calculates using light. Transistors, the workhorse of modern computers, aren't improving at the rate they once were. To scale AI, companies are building increasingly large and energy-expensive data centers—a path that is neither financially nor environmentally sustainable. By delivering ultra-high performance and energy efficiency, Lightmatter’s compute engine will power rapid advancements in AI while lowering its environmental footprint.

Lightmatter is looking for a Senior Power Integrity engineer to drive the next generation products from concept to development. You will be part of the cross-functional systems and packaging team consisting of silicon, package and systems engineers and tasked with driving the package and system architecture definition from concept, through design optimization and completion to meet the product’s power integrity requirements. This position offers a unique opportunity to innovate new package and system architectures by solving complex interaction across digital, analog and photonics domains while meeting stringent signal and power integrity goals. 

Responsibilities

• Design the end-to-end power delivery network (PDN) for digital and analog SoC domains, from the voltage regulator to the on-chip decoupling.
• Model voltage regulator switching ripple, bandwidth, and transient response and aid in the selection of power stages, controllers, and associated passives.
• Simulate PCBs and packages in commercial 2.5D electromagnetics simulators to extract N-port models and subsequently, impedance profiles. 
• Perform time domain simulations of supply rails to characterize worst case droops and overshoots.
• Perform detailed power integrity measurements and characterization using lab equipment, for example, using programmable loads to measure the transient response of the power delivery network.
• Collaborate with cross-functional teams such as hardware designers, PCB layout engineers, system architects, and power and performance engineers to provide power integrity guidance and support throughout the product development lifecycle.
• Contribute to power integrity design reviews, providing technical expertise and recommendations to ensure optimal power integrity performance, and adherence to design specifications.
• Document and communicate analysis results, design guidelines, and recommendations to stakeholders, including design teams, management, and customers.
• Participate in cross-functional teams to define and influence system-level architecture decisions that impact power integrity, ensuring optimal performance and scalability.

• Master's in Electrical Engineering or relevant field with 6 years of relevant experience, or Bachelor’s degree with 8 years of related experience in power delivery and power integrity analysis for high performance CPUs and compute SoCs. 
• Proficiency in using simulation and analysis tools for power integrity, including PowerSI, PowerDC, H-Spice, and ADS. 
• Experience with DC-DC converter design.

• Experience with PCB design and layout considerations for power integrity, including layer stack-up assignment, power plane partitioning, capacitor selection and placement, and microvia/PTH design. 
• Strong problem-solving and debugging skills for power integrity-related issues.
• Excellent communication skills, both verbal and written, to effectively collaborate with cross-functional teams and present findings to stakeholders.
• Ability to work independently and manage multiple projects simultaneously.

Preferred Qualifications

• Working knowledge of different 2D/2.5D/3D packaging technologies and associated PDN challenges.
• Familiarity in using lab equipment for signal measurement and characterization, such as oscilloscopes and network analyzers.
• Proficiency in scripting languages such as SKILL, TCL, Python, or Matlab for automation of design and modeling flows and post-processing results.