Packaging Architect

Location: Mountain View, CA

Department: Photonics Packaging Engineering

About This Role

As a Packaging Architect, you will own the development of advanced packaging solutions from concept through product release, partnering with cross-functional teams across substrate design, signal integrity, and power integrity. Working directly with product architects, chip designers, and system architects, you will translate complex technical requirements into precise packaging specifications that balance performance, cost, and manufacturability.

You will serve as a key technical decision-maker, driving architecture trade-offs, aligning stakeholders, and ensuring packaging solutions meet both engineering and business objectives across the full product lifecycle.

Responsibilities

• Evaluate and execute trade-offs across EIC/PIC layouts, die-to-die interfaces, fiber attachment methods, and packaging technologies, analyzing impact on performance, power efficiency, cost, manufacturability, and form factor.
• Define and own packaging specifications spanning electrical, thermal, and mechanical performance, ensuring alignment with project budget and schedule.
• Determine optimal package architecture through rigorous analysis of competing design constraints across the silicon, package, and system levels.
• Partner with supply chain engineering to define technology and material requirements for substrate fabrication, assembly, and raw material vendors.
• Collaborate with Quality & Reliability (Q&R) teams on packaging requirements, qualification criteria, and issue resolution.
• Engage with product teams and customers in the data center and high-performance compute segments to anticipate emerging packaging architectures and influence roadmap direction.
• Monitor the competitive landscape in packaging technologies to inform strategic and technical decisions.

Required Qualifications

• Ph.D. or Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field.
• 15+ years of experience in advanced (2D/3D) packaging technologies, with exposure to optical packaging.
• 10+ years of deep expertise in one or more of the following domains: power/signal integrity, thermal-mechanical analysis, or optical packaging.
• Demonstrated ability to perform system-level trade-offs across silicon, package, and board to define packaging technology solutions for complex products.
• Extensive experience with high-speed interfaces including SERDES, PCIe, and die-to-die (D2D) interconnects, and their implications for substrate selection, interconnect architecture, signal integrity, and thermal management.
• Proven track record of delivering successful packages and products from concept through production release.
• Proficiency with industry-standard EDA and CAD tools.

Preferred Qualifications

• Strong communication and collaboration skills, with experience working across engineering, supply chain, and external supplier organizations.
• Technical leadership experience managing complex, multi-disciplinary projects under demanding technical and schedule constraints.
• Ability to operate independently, drive decisions with minimal supervision, and manage ambiguity effectively.
• Creative problem-solver with a track record of finding practical solutions under pressure.