Staff IP Design Engineer (Functional Safety)

Location: Bayan Lepas, Penang, UNAVAILABLE, MY

Employment Type: FULL_TIME

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

A successful candidate will join a team designing and developing Lattice Foundation IP at Penang to help establish long-term capability in IP-level Functional Safety readiness and product robustness. The candidate will lead research, design and development of safety qualification of Foundation IP and/or safety-relevant aspects of FPGA EDA design flow, ensuring alignment with with product, quality and Functional Safety requirements. The candidate is expected to work closely with cross-functional teams to plan and execute Lattice Foundation IP release cycle including requirement analysis, feature scoping, safety impact assessment, development, testing, validation and release sign-off. Responsibilities & Skills

• Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields with 8+ years of experience in SoC and/or FPGA IP development.

Experience

• Strong communication skills.
• Knowledge or experience in FPGA architecture and FPGA software tools, specifically for device modeling and soft IP development.
• Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.

 

Preferred

• Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
• Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus.

Behaviors/Motivations

• Technical leadership: Serves as a recognized technical leader who influences cross organization engineering decisions/efforts.
• Accountability: Owns outcomes spanning multiple projects or releases, balancing short term delivery with long term technical health.
• Execution: Anticipates organizational and technical risks and drives alignment across teams to resolve them.
• Mentorship: Creates leverage by mentoring engineers, setting technical direction, and establishing best practices adopted broadly.