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Senior Staff RTL Verification Engineer

Jobgether

United States
Full-time
Senior
Staff
12+ yrs
$159k–$238kPosted 20h ago

Real job — pulled straight from Jobgether’s careers page · Verified August 12, 2026 · No reposts.

Job description

Jobgether is hiring a Senior Staff RTL Verification Engineer — a full-time, based in United States role ($159k–$238k). Apply directly on Jobgether's careers page below.

Senior Staff RTL Verification Engineer

Team: IT

Location: US

Commitment: Full-time

Workplace Type: remote

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff RTL Verification Engineer based in the United States.

The Senior Staff RTL Verification Engineer will play a critical role in verifying next-generation RAIN RFID Reader ICs from architecture through tape-out and production.
You will help define advanced verification methodologies, infrastructure, and coverage strategies for complex digital subsystems.
The role combines hands-on SystemVerilog and UVM development with technical leadership across verification, logic, analog, test, and systems engineering.
You will work on sophisticated microcontroller architectures, finite-state machines, bus functional models, behavioral models, and reusable verification environments.
A major focus will be improving verification efficiency through automation, CI/CD workflows, custom tooling, assertions, and comprehensive functional coverage.
This is an opportunity to influence verification practices while contributing to products that connect physical objects to digital systems at massive scale.
The position is remote-eligible in the United States, with Seattle also available as a work location, subject to role and state availability.

Accountabilities

    • Drive RTL verification activities for next-generation RAIN RFID Reader ICs across the full product development lifecycle, from early architecture through tape-out and production.
    • Define and implement modern verification methodologies, infrastructure, and processes that improve design quality, coverage, and development efficiency.
    • Develop SystemVerilog testbenches, bus functional models, subsystem behavioral models, architectural checkers, reusable sequences, and other verification components.
    • Create and execute both directed and constrained-random tests to validate complex functionality and achieve comprehensive functional coverage.
    • Develop detailed verification plans and establish coverage metrics that provide confidence in design quality and tape-out readiness.
    • Write SystemVerilog assertions, coverage monitors, and other automated checks to identify functional issues early and strengthen verification completeness.
    • Develop CI/CD workflows, custom verification toolkits, and reporting solutions that automate repetitive tasks and improve overall verification productivity.
    • Collaborate closely with digital logic, analog, test, systems, and other engineering teams to define requirements, resolve issues, and deliver new features and products.
    • Support ongoing enhancements to existing products, including feature additions, performance improvements, and verification updates.
    • Contribute technical leadership to verification strategy, methodology improvements, and best practices across complex IC development programs.
    • Requirements

      • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 12+ years of relevant experience; alternatively, 8+ years with a master's degree or 5+ years with a PhD.
      • 12+ years of professional experience in RTL verification, including experience taking complex semiconductor designs through tape-out and production.
      • Strong experience verifying microcontroller microarchitectures, complex finite-state machines, and sophisticated digital subsystems.
      • Proven ability to create and implement comprehensive RTL functional verification plans for complex IC designs.
      • Hands-on experience developing bus functional models, subsystem behavioral models, architectural checkers, and reusable verification infrastructure.
      • Advanced proficiency in SystemVerilog and the Universal Verification Methodology (UVM).
      • Strong experience developing SystemVerilog assertions, reusable sequences, coverage monitors, and functional coverage strategies.
      • Experience defining verification metrics and using coverage analysis to assess design completeness and tape-out readiness.
      • Familiarity with CI/CD systems and RTL coverage tools, with a demonstrated interest in improving verification automation and efficiency.
      • Scripting proficiency in Python, Perl, Ruby, UNIX shell, or comparable automation languages.
      • Strong analytical and problem-solving skills, with the ability to investigate complex verification issues and collaborate across engineering disciplines.
      • Excellent written and verbal communication skills, with the ability to explain technical issues and influence decisions across multidisciplinary teams.
      • Ability to work independently while contributing effectively within a highly collaborative semiconductor engineering environment.
      • Because the position involves technologies or data subject to U.S. export-control regulations, additional documentation regarding nationality or citizenship may be required to determine export compliance.
      • Benefits

        • Competitive compensation: Typical U.S. base salary range of $158,700–$238,100, with individual offers determined by factors including role complexity, responsibilities, relevant experience, skills, and market conditions.
        • Performance-based rewards: Eligible employees may receive merit increases, annual bonuses, and stock-based compensation based on individual performance and applicable plans.
        • Healthcare: Access to healthcare benefits, with available programs including medical coverage and other employee benefits.
        • Retirement savings: 401(k) plan with company matching.
        • Remote work: Remote-eligible opportunities in the United States, with flexibility depending on role and state availability.
        • Work-life balance: Open paid time-off policy designed to support flexibility and sustainable work practices.
        • Collaborative culture: An environment that emphasizes innovation, teamwork, openness, knowledge sharing, and recognition of accomplishments.
        • Professional growth: Opportunities to work with advanced semiconductor technologies, modern verification methodologies, and multidisciplinary engineering teams.
        • Meaningful work: The opportunity to contribute to technology that enables connected devices and real-world objects to interact with digital systems.
        • Inclusive workplace: Commitment to a diverse, equitable, and inclusive work environment, with reasonable accommodations available throughout the hiring process and employment.
How Jobgether works:
We use an AI-powered matching process to ensure your application is reviewed quickly, objectively, and fairly against the role's core requirements. Our system identifies the top-fitting candidates, and this shortlist is then shared directly with the hiring company. The final decision and next steps (interviews, assessments) are managed by their internal team.
We appreciate your interest and wish you the best!
 Why Apply Through Jobgether? 
 
Data Privacy Notice: By submitting your application, you acknowledge that Jobgether will process your personal data to evaluate your candidacy and share relevant information with the hiring employer. This processing is based on legitimate interest and pre-contractual measures under applicable data protection laws (including GDPR). You may exercise your rights (access, rectification, erasure, objection) at any time.
 
 
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Frequently asked questions

What is the salary for Senior Staff RTL Verification Engineer at Jobgether?

The estimated salary range for Senior Staff RTL Verification Engineer at Jobgether is $159,000 - $238,000 USD per year.

What skills are required for Senior Staff RTL Verification Engineer at Jobgether?

The required skills for Senior Staff RTL Verification Engineer at Jobgether include: SystemVerilog, Python, Perl, Ruby, Bash, CI/CD.

What is the seniority level for Senior Staff RTL Verification Engineer at Jobgether?

Senior Staff RTL Verification Engineer at Jobgether is a Senior / Staff level position.

How do I apply for Senior Staff RTL Verification Engineer at Jobgether?

You can view the full description and apply for Senior Staff RTL Verification Engineer at Jobgether on EchoJobs: https://echojobs.io/job/jobgether-senior-staff-rtl-verification-engineer-3i2y6.