Job Details:

Job Description: 

This position is within the Design Technology Platform (DTP) organization of Technology Development. At Intel, Design Technology Platform and Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies. As part of the Design Technology Platform / Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers. In this role you will be the experienced technical contributor in developing advanced PDK ESD protection verification solution on Intel's process technologies, including but not limited to: (i) Complete breadth coverage across multiple EDA PERC verification platforms (Cadence Pegasus, Siemens Calibre and Synopsys ICV). (ii) Continuous advancement of holistic ESD protection verification methodology and solution. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. Interaction with Process Development Teams, and EDA vendors is expected on a frequent basis in order enable production level verification solutions. #designenablement

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must possess a BS degree with 5+ years of experience or MS degree with 4+ years of experience or PhD degree with 3+ years of experience in Electronics Engineering, Electrical Engineering and Computer Engineering or related field. 3+ years of experience in one the following: - DRC/LVS runset development in Calibre-SVRF, ICV-PXL, or Pegasus language. - EDA PERC (Programmable Electrical Rules Check) rule deck development. - ESD protection verification solution development in PERC or Static ESD verification. - Scripting in Python, PERL or TCL. Preferred Qualifications: 3+ years of experience in the following: PDK development. IC physical design, layout, and/or verification flows. C++ based EDA tool/software development. Knowledge of IC manufacturing process flows . Exposure to CAD/CAE environments involving circuit simulation, physical verification, parasitic extraction, P2P resistance, current density analysis and/or netlisting tools. Software development practices such as Agile and Test Driven Development. Experience with various reliability verification tools - Ansys Totem / RedHawk / HFSS, Cadence Voltus-FI / Voltus, and/or Synopsys PrimSim.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.