Senior Manager, Analog & Mixed-Signal Design Engineering

Location: US, Arizona, Phoenix

Time Type: Full time

Job Description

Job Details:

Job Description: 

About the Role

The Hard IP and Test Chip Development team within Intel's Central Engineering Group (CEG) is responsible for delivering industry-leading analog and mixed-signal IP for Intel's Client, Data Center, AI, and Foundry businesses. The I/O team develops high-speed serial I/O and die-to-die interconnect solutions across advanced process technologies, enabling next-generation computing platforms.

As a Senior Manager, Analog & Mixed-Signal Design Engineering, you will lead a team responsible for developing cutting-edge analog IP and silicon solutions that shape Intel's future in high-speed connectivity, chiplet architectures, and advanced interconnect technologies.

This is a highly visible leadership role offering the opportunity to influence critical technologies, partner across multiple engineering organizations, and drive execution on products that are foundational to Intel's future. Candidates will gain exposure across the complete product lifecycle, from architecture and design through silicon validation and production readiness, while helping grow and develop a team of talented engineers.

What You’ll Do:

Key responsibilities will include but not limited to:

Technical Leadership

• Lead the development and delivery of analog and mixed-signal IP including ADCs, DACs, phase interpolators, voltage regulators, clocking circuits, and other high-performance analog building blocks.
• Drive technical excellence throughout the product lifecycle, including architecture reviews, design execution, verification, silicon bring-up, validation, and product readiness.
• Partner with senior technical leaders to establish technical direction and align organizational priorities with product roadmaps.
• Promote engineering innovation through automation, process optimization, and AI-assisted engineering methodologies.

Program & Execution Leadership

• Develop execution strategies and project plans that enable successful delivery of IP and SoC milestones.
• Manage schedules, resources, risks, dependencies, and deliverables across multiple concurrent development efforts.
• Leverage data-driven insights to communicate progress, support decision-making, and drive successful business outcomes.
• Ensure alignment across geographically distributed teams and stakeholders.

Team Leadership & Talent Development

• Build, lead, and develop a high-performing organization of analog and mixed-signal design engineers.
• Recruit, coach, mentor, and retain top engineering talent.
• Foster an inclusive culture that promotes innovation, collaboration, accountability, and continuous learning.
• Develop future technical and organizational leaders through active coaching and professional development.

Cross-Functional Collaboration

• Partner closely with architecture, design, validation, physical design, layout, product engineering, manufacturing, and program management teams.
• Collaborate across Intel organizations to deliver complete end-to-end solutions and drive successful product outcomes.
• Work with global engineering teams, including collaboration across U.S. and India-based partners, to achieve shared goals and execution milestones.

Organizational Impact

• Drive organizational excellence through strong leadership, execution discipline, and operational rigor.
• Influence strategic decisions while balancing technical, business, and organization priorities.
• Help shape future technology directions that enable Intel's next generation of AI, client, datacenter, and foundry solutions.

Behavioral traits that we are looking for:

• Strategic Leadership: Develops and executes a clear technical vision while balancing long-term strategy with business and execution priorities.
• Talent Development: Builds high-performing teams by coaching, mentoring, and fostering the growth of engineers at all career stages
• Collaboration & Influence: Effectively partners across organizations and influences stakeholders to achieve shared technical and business objectives.
• Ownership & Accountability: Takes responsibility for delivering results, driving execution excellence, and resolving complex challenges.
• Innovation Mindset: Champions continuous improvement, embraces new technologies, and drives innovation through efficient engineering practices.
• Communication Excellence: Communicates technical and business concepts clearly while building trust and alignment across diverse audiences.

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. 

See Intel Benefits for more details. 

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. 

Note:

• This position is not eligible for Intel immigration sponsorship.

• This is an on-site role and you are expected to work in the office at least 4 days per week.​

Minimum Qualifications and Experience:

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 9+ years of experience.
• 6+ years of experience in a people leadership, technical leadership, project leadership, or management role within a matrixed organization.
• 8+ years of experience delivering analog or mixed-signal IP from concept through silicon validation and product deployment.
• 7+ years of experience with analog design fundamentals, including noise, jitter, matching, stability, linearity, and/or performance optimization
• 7+ years of experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits. 

Preferred Qualifications and Experience:

• Master's degree in Electrical Engineering, Electronics Engineering, or related field with 6+ years of experience.
• Experience managing analog IP design teams.
• Experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, Transmitter (TX) design, or Receiver (RX) design.
• Knowledgeable about high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe.
• Building, leading, and driving execution in silicon teams delivering to complex, high-impact programs.

Why Join Intel? Join Intel to lead the development of industry-leading analog and mixed-signal technologies that power the future of AI, high-performance computing, and next-generation connectivity, while collaborating with world-class engineering teams and influencing products delivered at global scale.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.