Senior Logic Design Engineer
Location: US, California, Santa Clara
Time Type: Full time
Job Description
Job Details:
Job Description:
The Role and Impact:
At Intel, we are driving cutting-edge innovation to transform technology and enrich lives globally. As an IP Logic Design Engineer, you will play a critical role in developing next-generation products and standard IPs that lead the industry in speed, efficiency, and cost-effectiveness. You will contribute to the development of silicon solutions that empower people's digital lives and address complex technical challenges that redefine technology. Your work will directly impact the integration and verification of world-class IP blocks into full chip designs, ensuring they meet strict quality and performance standards.
Join us in pushing boundaries and driving innovation to build something truly wonderful.
Key Responsibilities:
Develop logic design, register transfer level (RTL) coding, and simulation for IP blocks and subsystems for integration in full chip designs
Define architecture and microarchitecture features and ensure their implementation in the block being designed
Optimize design logic to meet power, performance, area, and timing goals while maintaining design integrity for physical implementation
Review the verification plan and implementation to ensure design features are verified accurately and resolve issues in failing RTL tests
Drive quality assurance compliance to enable smooth IP-SoC handoff for high-quality integration and verification of IP blocks.
Collaborate with cross-functional teams to address security threat models and implement secure development practices within the design
Support SoC-level integration by working with IP providers to validate IPs and ensure seamless functionality
Strong communication and collaboration skills, with the ability to influence and inspire cross-functional teams
Qualifications:
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related STEM field
6+ years of experience with RTL design and System Verilog
2+ years of experience in Advanced Microcontroller Bus Architecture (AMBA) protocols and coherent protocols such as CHI
Experience in hardware design, including logic design, state machines, control units, processor subsystems, and network-on-chip architectures
Experience with industry-standard tools and flows for front-end design, including one or more of the following (synthesis, static timing analysis (STA), and/or Spyglass-based checks.)
Preferred Qualifications
Post Graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field
Experience working on high-speed interconnects and In-Die Interface (IDI) protocol
Programming skills in languages such as Python or Perl
We invite you to be part of a team that is breaking through innovation and driving technology advancement every day. Apply today to make a meaningful impact with your expertise and passion.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.There are more than 50,000 engineering jobs:
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