Job Details:

Job Description: 

Exciting opportunity to be a part of XNE DFT team. The Design-for-Test (DFT) Implementation Engineer is a challenging and cutting-edge position working as part of a team to implement Design-for-Test capabilities on state-of-the-art silicon designs. You will be working with both external tier-1 customers and internal product design teams during their ASIC design cycle as they develop System-on-a-Chip (SoC) solutions utilizing CMOS cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high speed memory interface IP. You will be responsible for development of the SoC Test Implementation plan describing the strategies to address the DFT requirements for the design, planning of the hierarchical test architecture, insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for HVM ATE testing of the design, supporting the Static Timing Analysis (STA) team for the timing closure for the DFT modes of the design, and for supporting the Test Engineering team during silicon bring-up and New Product Introduction (NPI). You will also work closely with internal Test Methodology team and IP development teams.

Qualifications:

Minimum Qualifications:

The candidate must possess a Bachelors 7+ years of experience or MS in Electrical or Computer Engineering 5+ years of experience in:

- SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN
- DFT architecture development and planning for an SoC
- Test insertion, test pattern generation, simulation, and validation
- Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax
- Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug
- Scripting Languages, e.g., PERL, TCL/Tk, Python.

- Intermediate English level, verbal & written.

Preferred Qualifications:

- Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience
- Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Costa Rica)

Primary Location: 

Costa Rica, San Jose

Additional Locations:

Business group:

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.