Platform Integration Engineer

Location: US, California, Santa Clara, US, Oregon, Hillsboro, US, California, Folsom, US, Texas, Austin

Time Type: Full time

Job Description

Job Details:

Job Description: 

Intel is seeking an experienced Platform Integration Engineer and Micro Architect for the Intel Chassis Group. The Chassis Group is chartered to deliver the chassis for multiple SoCs within Intel.

The role involves

• Working with the SoC architecture teams to understand the SoC chassis requirements
• Designing and developing high-performance networks-on-chip which meet the SoC PPA requirements
• Coordinating with the foundation IP development team within the Chassis Group to modify/create IP components as per SoC needs

Qualifications:

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel's immigration sponsorship.

Minimum Qualifications

• Bachelor's in Science, Electrical Engineering or equivalent with 5+ years experience – OR – Master's  degree in Science, Electrical Engineering or equivalent with 4+ years experience
• Experience in SOC and/or IP design
• Experience in SoC interconnect design and microarchitecture, coherent and non-coherent fabrics, AMBA/PCIe/CXL protocols and memory subsystems.

Preferred Qualifications

• 8+ years of experience in:
  • SOC and/or IP design
  • Microarchitecture and design of IP sub-systems including 5+ years' experience in fabrics for AI SoCs
• Expertise in Verilog/System Verilog, Lint/CDC/RDC
• Expertise in AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL
• Experience in designing credit-based interconnect systems with QoS, security, debug/trace and RAS
• Good understanding of coherency concepts
• Experience in analyzing power, performance and area trade-offs in designs
• Experience in working with architecture, verification, formal verification, emulation and firmware teams
• Ability to work with physical design to understand floor plan constraints and optimize fabric design based on these requirements
• Experience with leading edge process nodes
• Good understanding of memory subsystems including HBM and LPDDR
• Strong communication skills
• Demonstrated ability to work across large, geographically distributed engineering teams across multiple time zones

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.