Job Details:

Job Description: 

DE Custom Design team is working on latest technology node and low power design. Focus of your work is to influence the design enablement delivering leadership PDK for cutting edge technology and design, deliver a low power SoC testchip and product. You will be given the opportunity to work on high performance and low power SoC design from RTL to GDSII. Collaborate with PDK, Std Cells library, and FE RTL teams to deliver cutting edge design on Intel's best technology node.


Our Custome Design team is looking for a high caliber Physical Design Engineer to contribute to high performance/low power partitions using best methods in synthesis, placement, and route. In addition to running all back-end validation and verification tools.

Your responsibility will include but not limited to:

- Block level floor-planning.
- Voltage area and power grid implementation.

- Implementation of APR flows using Synopsys Fusion Compiler tool.
- Static Timing Analysis using Synopsys PrimeTime
- Power Analysis and power optimization using RedHawk and PTPX.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must be pursuing a Master's or Ph.D. degree in Electrical Engineering or a related STEM degree.

Theoretical knowledge or qualifying course work in SOC design flows: Synthesis, APR, STA, and physical verifications. Strong programming skillset in TCL, Perl, or Python.

Preferred Qualifications:

• VLSI circuits, design techniques.

• Designing high-speed, low-power digital circuits, floor planning, timing convergence and layout verification

• Logic synthesis and automated place and route tools

• Logic design fundamentals

• Hardware description languages such as Verilog or System Verilog

          

Job Type:

Student / Intern

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Texas, Austin

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$63,000.00-$166,000.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.