Job Details:

Job Description: 

Deliver industry standard parasitic extraction tools / flows and capabilities for Intel's Customers. Primary responsibility includes but not limited to enablement of PDK Custom and ASIC extraction flows/ methodologies and test the PDK collaterals. Job function includes assuring the quality of Extraction decks by setting up various flows/methodologies. Should be self-driven and able to take up new tasks. Should closely interact with EDA vendors for enablement of new features / additions to the existing flows / methodologies. Provide support for internal customers, collaborate with EDA vendors for enhancement of the flows based on customer requests. Should be proficient in documenting the observations made from the flows executed. Automation of the key capabilities for design productivity is add-on responsibility. Interfacing with PDK teams, EDA vendors, contracting employees from design service partners is a day-to-day job function.

Qualifications:

Candidate should have minimum of B.E with 5+ years (or) M.E with 3+ years of experience in custom layout design methodology and ASIC physical design / PnR flow. Must have worked on industry standard tools for extraction, like Star-RC / QRC, Cadence virtuoso / Synopsys Custom Designer, Cadence Innovus / Synopsys ICC2 tools with relative design experience. Candidate should be well versed with different parameters to optimize flow in terms of quality and resources. Candidate should have good knowledge on semiconductor physics, process technology, EDA tools and associated challenges for advance technology. Must be proficient in automation using skill, tcl, python, perl and other scripting languages. Candidate should be flexible to work on different aspects of PDK deliverables. Good in written and verbal communication skills.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.