Mixed Signal Logic Design Engineer

Location: India, Bangalore

Time Type: Full time

Job Description

Job Details:

Job Description: 

• The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations for the cutting-edge DDRPHY IPs.
• You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools for Lint, CDC, RDC, Voltage domain crossings, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc.
• You will also have an opportunity to contribute to automating various Front End Tool, Flows and Methodologies and innovating the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams.
• The ideal candidate should exhibit excellent written and verbal communication skills which are critical in a small, fast-moving team. As part of a growing, dynamic business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.

Objectives of the position
- Own and deliver the logic design of Mixed Signal IPs.
- Continuously drive improvement in the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements.
- Drive area/power of IPs and come up with improvements on IP Area/Power metrics.
- Critical Decision making on Technical issues.

Qualifications:

Minimum Qualifications
- The successful candidate will possess a BS, MS degree with a 10+ years of relevant industry experience.
- Proficiency in RTL design and coding using System Verilog and Verilog.
- Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating.
- Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
- Experience with hardware simulation tools and methodologies (VCS/Verdi).
- Familiarity with IP environment and configuration management tools.
- Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low power design.

Preferred Qualifications
- Demonstrated ability to debug complex logic designs, speed paths and validate system-level functionality.
- Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic team environment.
- Strong problem-solving skills, disciplined execution, and a proactive mindset.
- DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols.
- VSCode GitHub CoPilot or any other AI experience.
- Exposed to Formal Property Verification and Git version control.
- Ability to drive an optimal solution between analog and digital designs.
- Familiarity with pre-silicon and post-silicon validation.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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